Datasheet

SPI
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
236 Document Number: 333577-002EN
15.3.1.3 SSI Enable Register (SSIENR)
MEM Offset (B0001000) 08h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bits Access
Type
Default Description PowerWell ResetSignal
31:1 RO 31'b0 Reserved 1 (RSVD1)
Reserved
0 RW 1'h0 SSI Enable (SSIENR)
Enables and disables all SPI
Controller operations. When
disabled, all serial transfers
are halted immediately.
Transmit and receive FIFO
buffers are cleared when the
device is disabled. It is
impossible to program some of
the SPI Controller control
registers when enabled. When
disabled, the ssi_sleep output
is set (after delay) to inform
the system that it is safe to
remove the ssi_clk, thus
saving power consumption in
the system.
15.3.1.4 Microwire Control Register (MWCR)
This register controls the direction of the data word for the half-duplex Microwire serial
protocol. It is impossible to write to this register when the SPI Controller is enabled.
The SPI Controller is enabled and disabled by writing to the SSIENR register.
MEM Offset (B0001000) 0Ch
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bits Access
Type
Default Description PowerWell ResetSignal
31:3 RO 29'b0 Reserved 1 (RSVD1)
Reserved