Datasheet

SPI
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 235
Bits Access
Type
Default Description PowerWell ResetSignal
3:0 RO 4'b0 Reserved 1 (RSVD1)
Reserved
15.3.1.2 Control Register 1 (CTRLR1)
This register exists only when the SPI Controller is configured as a master device.
When the SPI Controller is configured as a serial slave, writing to this location has no
effect; reading from this location returns 0. Control register 1 controls the end of
serial transfers when in receive-only mode. It is impossible to write to this register
when the SPI Controller is enabled. The SPI Controller is enabled and disabled by
writing to the SSIENR register.
MEM Offset (B0001000) 04h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bits Access
Type
Default Description PowerWell ResetSignal
31:16 RO 16'b0 Reserved 1 (RSVD1)
Reserved
15:0 RW/L 16'h0 Number of Data Frames
(NDF)
When TMOD = 10 or TMOD =
11, this register field sets the
number of data frames to be
continuously received by the
SPI Controller. The SPI
Controller continues to
receive serial data until the
number of data frames
received is equal to this
register value plus 1, which
enables you to receive up to
64 KB of data in a continuous
transfer. When the SPI
Controller is configured as a
serial slave, the transfer
continues for as long as the
slave is selected. Therefore,
this register serves no
purpose and is not present
when the SPI Controller is
configured as a serial slave.