Datasheet

SPI
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 231
15.3.1.1 Control Register 0 (CTRLR0)
This register controls the serial data transfer. It is impossible to write to this register
when the SPI Controller is enabled. The SPI Controller is enabled and disabled by
writing to the SSIENR register.
MEM Offset (B0001000) 00h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0007_0000h
Bits Access
Type
Default Description PowerWell ResetSignal
31:21 RO 11'b0 Reserved 2 (RSVD2)
Reserved
20:16 RW/L 5'h07 Data Frame Size in 32-bit
mode (DFS_32)
Used to select the data frame
length in 32 bit mode. These
bits are only valid when
SSI_MAX_XFER_SIZE is
configured to 32. When the
data frame size is
programmed to be less than
32-bits, the receive data is
automatically right-justified
by the receive logic, with the
upper bits of the receive FIFO
zero-padded. Transmit data
must be right-justified by the
user before writing into the
transmit FIFO. The transmit
logic will ignore the upper
unused bits when
transmitting the data.
15:12 RW/L 4'h0 Control Frame Size (CFS)
Control Frame Size. Selects
the length of the control word
for the Microwire* frame
format.
11 RW/L 1'h0 Shift Register Loop (SRL)
Used for testing purposes
only. When internally active,
connects the transmit shift
register output to the receive
shift register input. Can be
used in both serial-slave and
serial-master modes.
0 : Normal Mode Operation
1 : Test Mode Operation