Datasheet

SPI
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 229
15.3 Memory Mapped IO Registers
Registers listed are for SPI Master 0, starting at base address B0001000h.
SPI Slave 0 contains the same registers starting at base address B0001800h.
Differences between the SPIs are noted in individual registers.
Table 37. Summary of SPI Registers—0xB0001000 & 0xB0001800
MEM
Address
Default Instance Name Name
0x00 0007_0000h CTRLR0 Control Register 0
0x04 0000_0000h CTRLR1 Control Register 1
0x08 0000_0000h SSIENR SSI Enable Register
0x0C 0000_0000h MWCR Microwire Control Register
0x10 0000_0000h SER Slave Enable Register
0x14 0000_0000h BAUDR Baud Rate Select
0x18 0000_0000h TXFTLR Transmit FIFO Threshold Level
0x1C 0000_0000h RXFTLR Receive FIFO Threshold Level
0x20 0000_0000h TXFLR Transmit FIFO Level Register
0x24 0000_0000h RXFLR Receive FIFO Level Register
0x28 0000_0006h SR Status Register
0x2C 0000_003Fh IMR Interrupt Mask Register
0x30 0000_0000h ISR Interrupt Status Register
0x34 0000_0000h RISR Raw Interrupt Status Register
0x38 0000_0000h TXOICR Transmit FIFO Overflow Interrupt Clear
Register
0x3C 0000_0000h RXOICR Receive FIFO Overflow Interrupt Clear
Register
0x40 0000_0000h RXUICR Receive FIFO Underflow Interrupt Clear
Register
0x44 0000_0000h MSTICR Multi-Master Interrupt Clear Register
0x48 0000_0000h ICR Interrupt Clear Register
0x4C 0000_0000h DMACR DMA Control Register
0x50 0000_0000h DMATDLR DMA Transmit Data Level
0x54 0000_0000h DMARDLR DMA Receive Data Level
0x58 0000_0000h IDR Identification Register
0x5C 3332_332A
h
SSI_COMP_VERSI
ON
coreKit Version ID register
0x60 0000_0000h DR0 Data Register
0x64 0000_0000h DR1 Data Register