Datasheet

UART
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
224 Document Number: 333577-002EN
14.3.1.20 Line Extended Control Register (LCR_EXT)
Line Extended Control Register.
MEM Offset (B0002000) 0B00020CCh
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bits Access
Type
Default Description PowerWell ResetSignal
31:4 RO 28'b0 Reserved (RSV)
3 RW 1'h0 Transmit mode control bit
(TRANSMIT_MODE)
Transmit mode control bit.
This bit is used to control the
type of transmit mode during
9-bit data transfers.
1 : In this mode of operation,
Transmit Holding Register
(THR) and Shadow Transmit
Holding Register (STHR) are
9-bit wide. The user needs to
ensure that the THR/STHR
register is written correctly for
address/data.
Address: 9th bit is set to 1,
Data : 9th bit is set to 0.
NOTE: Transmit address
register (TAR) is not applicable
in this mode of operation.
0: In this mode of operation,
Transmit Holding Register
(THR) and Shadow Transmit
Holding register (STHR) are 8-
bit wide. The user needs to
program the address into
Transmit Address Register
(TAR) and data into the
THR/STHR register.
SEND_ADDR (LCR_EXT[10])
bit is used as a control knob to
indicate the UART Controller
on when to send the address.
2 RW/AC 1'h0 Send address control bit
(SEND_ADDRESS)