Datasheet

UART
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
220 Document Number: 333577-002EN
14.3.1.14 Receiver Output Enable Register (RE_EN)
Receiver Output Enable Register.
MEM Offset (B0002000) 0B00020B4h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bits Access
Type
Default Description PowerWell ResetSignal
31:1 RO 31'b0 Reserved (RSV)
0 RW 1'h0 Receiver Output Enable
(RE_Enable)
The RE Enable register bit is
used to control assertion and
de-assertion of re signal.
0: De-assert RE signal
1: Assert RE signal
14.3.1.15 Driver Output Enable Timing Register (DET)
Used to holds the DE assertion and de-assertion timings of the signal.
MEM Offset (B0002000) 0B00020B8h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bits Access
Type
Default Description PowerWell ResetSignal
31:24 RO 8'b0 Reserved (RSV1)
23:16 RW 8'h0 DE de-assertion time
(DE_deassertion_time)
DE signal de-assertion time.
This field controls the amount
of time (in terms of number
of serial clock periods)
between the end of stop bit
on the sout to the falling
edge of Driver output enable
signal.
15:8 RO 8'b0 Reserved (RSV0)