Datasheet

UART
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 219
Bits Access
Type
Default Description PowerWell ResetSignal
Receiver Enable Polarity.
1: RE signal is active high
0: RE signal is active low
0 RW 1'h0 RS485 Transfer Enable
(RS485_EN)
RS485 Transfer Enable.
0 : In this mode, the transfers
are still in the RS232 mode.
All other fields in this register
are reserved and registers
DE_EN, RE_EN, DET and TAT
are reserved.
1 : In this mode, the transfers
will happen in RS485 mode.
All other fields of this register
are applicable.
14.3.1.13 Driver Output Enable Register (DE_EN)
Driver Output Enable Register.
MEM Offset (B0002000) 0B00020B0h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bits Access
Type
Default Description PowerWell ResetSignal
31:1 RO 31'b0 Reserved (RSV)
0 RW 1'h0 Driver Output Enable
(DE_Enable)
The DE Enable register bit is
used to control assertion and
de-assertion of de signal.
0: De-assert de signal
1: Assert de signal