Datasheet

UART
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
218 Document Number: 333577-002EN
Bits Access
Type
Default Description PowerWell ResetSignal
0 : In this mode, transmit and
receive can happen
simultaneously. The user can
enable DE_EN, RE_EN at any
point of time. Turn around
timing as programmed in the
TAT register is not applicable
in this mode.
1 : In this mode, DE and RE
are mutually exclusive. Either
DE or RE only one of them is
expected to be enabled
through programming.
Hardware will consider the
Turn Around timings which are
programmed in the TAT
register while switching from
RE to DE or DE to RE. For
transmission Hardware will
wait if it is in middle of
receiving any transfer, before
it starts transmitting.
2 : In this mode, DE and RE
are mutually exclusive. Once
DE_EN/RE_EN is programed -
by default re will be enabled
and UART Controller controller
will be ready to receive. If the
user programs the TX FIFO
with the data then the UART
Controller, after ensuring no
receive is in progress, disables
the RE signal and enables the
DE signal.
Once the TX FIFO becomes
empty, RE signal gets enabled
and DE signal will be disabled.
In this mode of operation
hardware will consider the
Turn Around timings which are
programmed in the TAT
register while switching from
RE to DE or DE to RE. In this
mode, DE and RE signals are
strictly complementary to each
other.
2 RW 1'h1 Driver Enable Polarity
(DE_POL)
Driver Enable Polarity.
0: DE signal is active low
1: DE signal is active high
1 RW 1'h1 Receiver Enable Polarity
(RE_POL)