Datasheet

UART
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
214 Document Number: 333577-002EN
Bits Access
Type
Default Description PowerWell ResetSignal
0 RO 1'h0 Delta Clear to Send (DCTS)
Used to indicate that the
modem control line cts_n has
changed since the last time
the MSR was read. That is:
0 = no change on cts_n since
last read of MSR 1 = change
on cts_n since last read of
MSR
Reading the MSR clears the
DCTS bit. In Loopback Mode
(MCR[4] set to one), DCTS
reflects changes on MCR[1]
(RTS). Note, if the DCTS bit is
not set and the cts_n signal is
asserted (low) and a reset
occurs (software or
otherwise), then the DCTS bit
will get set when the reset is
removed if the cts_n signal
remains asserted.
14.3.1.8 Scratchpad (SCR)
Used by the programmer to hold data temporarily.
MEM Offset (B0002000) 0B000201Ch
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bits Access
Type
Default Description PowerWell ResetSignal
31:8 RO 24'b0 Reserved (RSV)
7:0 RW 8'h0 Scratchpad Register (SCR)
This register is for
programmers to use as a
temporary storage space. It
has no defined purpose in the
UART.