Datasheet

UART
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 213
Bits Access
Type
Default Description PowerWell ResetSignal
Reading the MSR clears the
DDCD bit. In Loopback Mode
(MCR[4] set to one), DDCD
reflects changes on MCR[3]
(Out2). Note, if the DDCD bit
is not set and the dcd_n signal
is asserted (low) and a reset
occurs (software or
otherwise), then the DDCD bit
will get set when the reset is
removed if the dcd_n signal
remains asserted.
2 RO 1'h0 Trailing Edge of Ring
Indicator (TERI)
Used to indicate that a change
on the input ri_n (from an
active low, to an inactive high
state) has occurred since the
last time the MSR was read.
That is:
0 = no change on ri_n since
last read of MSR
1 = change on ri_n since last
read of MSR
Reading the MSR clears the
TERI bit. In Loopback Mode
(MCR[4] set to one), TERI
reflects when MCR[2] (Out1)
has changed state from a high
to a low.
1 RO 1'h0 Delta Data Set Ready
(DDSR)
Used to indicate that the
modem control line dsr_n has
changed since the last time
the MSR was read. That is:
0 = no change on dsr_n since
last read of MSR 1 = change
on dsr_n since last read of
MSR
Reading the MSR clears the
DDSR bit. In Loopback Mode
(MCR[4] set to one), DDSR
reflects changes on MCR[0]
(DTR). Note, if the DDSR bit is
not set and the dsr_n signal is
asserted (low) and a reset
occurs (software or
otherwise), then the DDSR bit
will get set when the reset is
removed if the dsr_n signal
remains asserted.