Datasheet

UART
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
212 Document Number: 333577-002EN
Bits Access
Type
Default Description PowerWell ResetSignal
Used to indicate the current
state of the modem control
line dsr_n. That is this bit is
the complement dsr_n. When
the Data Set Ready input
(dsr_n) is asserted it is an
indication that the modem or
data set is ready to establish
communications with the
UART.
0 = dsr_n input is de-asserted
(logic 1)
1 = dsr_n input is asserted
(logic 0)
In Loopback Mode (MCR[4] set
to one), DSR is the same as
MCR[0] (DTR).
4 RO 1'h0 Clear to Send (CTS)
Used to indicate the current
state of the modem control
line cts_n. That is, this bit is
the complement cts_n. When
the Clear to Send input
(cts_n) is asserted it is an
indication that the modem or
data set is ready to exchange
data with the UART
0 = cts_n input is de-asserted
(logic 1)
1 = cts_n input is asserted
(logic 0)
In Loopback Mode (MCR[4] set
to one), CTS is the same as
MCR[1] (RTS).
3 RO 1'h0 Delta Data Carrier Detect
(DDCD)
Used to indicate that the
modem control line dcd_n has
changed since the last time
the MSR was read. That is:
0 = no change on dcd_n since
last read of MSR 1 = change
on dcd_n since last read of
MSR