Datasheet

UART
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
210 Document Number: 333577-002EN
Bits Access
Type
Default Description PowerWell ResetSignal
1 RO 1'h0 Overrun error bit (OE)
Used to indicate the
occurrence of an overrun
error. This occurs if a new
data character was received
before the previous data was
read. In the non-FIFO mode,
the OE bit is set when a new
character arrives in the
receiver before the previous
character was read from the
RBR. When this happens, the
data in the RBR is overwritten.
In the FIFO mode, an overrun
error occurs when the FIFO is
full and a new character
arrives at the receiver. The
data in the FIFO is retained
and the data in the receive
shift register is lost.
0 = no overrun error, 1 =
overrun error
Reading the LSR clears the OE
bit.
0 RO 1'h0 Data Ready bit (DR)
Used to indicate that the
receiver contains at least one
character in the RBR or the
receiver FIFO.
0 = no data ready, 1 = data
ready
This bit is cleared when the
RBR is read in the non-FIFO
mode, or when the receiver
FIFO is empty, in the FIFO
mode.