Datasheet

Physical Interfaces
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 21
2 Physical Interfaces
2.1 Pin States Through Reset
All functional IOs will come up in input mode after reset except JTAG TDO output
which is kept tristated.
All Digital IO include a configurable pullup (49K ohm typ; 34K-74Kohm range) with
pull-up disabled by default, except for F_20, F_22, F_23 pins (TRST_N, TMS, TDI))
where pull-up is enabled by default.
The state of all IOs is retained whenever SoC goes into low power states.
2.2 External Interface Signals
The following table gives the definition of external interface signals of Intel
®
Quark
microcontroller D2000. Not all interfaces are available simultaneously through
external pins of Intel
®
Quark™ microcontroller D2000. For pin multiplexing options,
refer to Chapter 3
.
Table 1. List of User Mode External Interfaces
Interface Pin Name Type Description
Power
VSS
QFN package ground plane
PVDD Supply 2.0-3.6 V unregulated battery
supply rail input (can lower to
1.8V if analog comparators are
not used). This rail is used only
by internal voltage regulator.
There is a mechanism to
disable internal voltage
regulator and feed
IOVDD/AVDD/DVDD by
platform directly. PVDD is to be
supplied even if Internal voltage
regulator is not enabled as
internal VR is used to generate
internal voltage reference for
comparators.
AVDD Supply 2.0-3.6V Analog Voltage Rail
Input powering both ADC and
Comparator - ADC supports
1.8V to 3.3V range, but
Comparator only supports 2V to
3.3V. AVDD can be an AC
isolated version of PVDD.