Datasheet

UART
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 209
Bits Access
Type
Default Description PowerWell ResetSignal
Used to indicate the
occurrence of a framing error
in the receiver. A framing
error occurs when the receiver
does not detect a valid STOP
bit in the received data. In the
FIFO mode, since the framing
error is associated with a
character received, it is
revealed when the character
with the framing error is at the
top of the FIFO. When a
framing error occurs the UART
will try resynchronize. It does
this by assuming that the
error was due to the start bit
of the next character and then
continues receiving the other
bit i.e. data, and/or parity and
stop. It should be noted that
the Framing Error (FE) bit
(LSR[3]) will be set if a break
interrupt has occurred, as
indicated by Break Interrupt
(BI) bit (LSR[4]).
0 = no framing error, 1 =
framing error
Reading the LSR clears the FE
bit.
2 RO 1'h0 Parity Error bit (PE)
Used to indicate the
occurrence of a parity error in
the receiver if the Parity
Enable (PEN) bit (LCR[3]) is
set. In the FIFO mode, since
the parity error is associated
with a character received, it is
revealed when the character
with the parity error arrives at
the top of the FIFO. It should
be noted that the Parity Error
(PE) bit (LSR[2]) will be set if
a break interrupt has
occurred, as indicated by
Break Interrupt (BI) bit
(LSR[4]).
0 = no parity error, 1 = parity
error
Reading the LSR clears the PE
bit.