Datasheet

UART
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
208 Document Number: 333577-002EN
Bits Access
Type
Default Description PowerWell ResetSignal
If THRE mode is disabled
(IER[7] set to zero) and
regardless of FIFO's being
enabled or not, this bit
indicates that the THR or TX
FIFO is empty. This bit is set
whenever data is transferred
from the THR or TX FIFO to
the transmitter shift register
and no new data has been
written to the THR or TX FIFO.
This also causes a THRE
Interrupt to occur, if the THRE
Interrupt is enabled.
If the THRE mode and FIFO
are enabled (IER[7] and
FCR[0] set to one), the
functionality is switched to
indicate the transmitter FIFO
is full, and no longer controls
THRE interrupts, which are
then controlled by the
FCR[5:4] threshold setting.
4 RO 1'h0 Break Interrupt bit (BI)
Used to indicate the detection
of a break sequence on the
serial input data. If in UART
mode it is set whenever the
serial input, sin, is held in a
logic '0' state for longer than
the sum of start time + data
bits + parity + stop bits.
A break condition on serial
input causes one and only one
character, consisting of all
zeros, to be received by the
UART. In the FIFO mode, the
character associated with the
break condition is carried
through the FIFO and is
revealed when the character is
at the top of the FIFO.
Reading the LSR clears the BI
bit. In the non-FIFO mode, the
BI indication occurs
immediately and persists until
the LSR is read.
3 RO 1'h0 Framing Error bit (FE)