Datasheet

UART
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 207
Bits Access
Type
Default Description PowerWell ResetSignal
In the FIFO mode, since the
9th bit is associated with a
character received, it is
revealed when the character
with the 9th bit set to 1 is at
the top of the FIFO.
Reading the LSR clears the
9BIT.
NOTE: User needs to ensure
that interrupt gets cleared
(reading LSR register) before
the next address byte arrives.
If there is a delay in clearing
the interrupt, then Software
will not be able to distinguish
between multiple address
related interrupt.
7 RO 1'h0 Receiver FIFO Error bit
(RFE)
This bit is only relevant when
FIFO are enabled (FCR[0] set
to one). This is used to
indicate if there is at least one
parity error, framing error, or
break indication in the FIFO.
That is:
0 = no error in RX FIFO
1 = error in RX FIFO
This bit is cleared when the
LSR is read and the character
with the error is at the top of
the receiver FIFO and there
are no subsequent errors in
the FIFO.
6 RO 1'h1 Transmitter Empty bit
(TEMT)
If FIFO are enabled (FCR[0]
set to one), this bit is set
whenever the Transmitter
Shift Register and the FIFO
are both empty.
If FIFO are disabled, this bit is
set whenever the Transmitter
Holding Register and the
Transmitter Shift Register are
both empty.
5 RO 1'h1 Transmit Holding Register
Empty bit (THRE)