Datasheet
UART
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
206 Document Number: 333577-002EN
Bits Access
Type
Default Description PowerWell ResetSignal
0 RW 1'h0 Data Terminal Ready (DTR)
Used to directly control the
Data Terminal Ready (dtr_n)
output. The value written to
this location is inverted and
driven out on dtr_n, that is:
0 = dtr_n de-asserted (logic
1)
1 = dtr_n asserted (logic 0)
The Data Terminal Ready
output is used to inform the
modem or data set that the
UART is ready to establish
communications. Note that in
Loopback mode (MCR[4] set
to one), the dtr_n output is
held inactive high while the
value of this location is
internally looped back to an
input.
14.3.1.6 Line Status (LSR)
Provides status information concerning the data transfer.
MEM Offset (B0002000) 0B0002014h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0060h
Bits Access
Type
Default Description PowerWell ResetSignal
31:9 RO 23'b0 Reserved (RSV)
8 RO/C 1'h0 Address Received bit
(ADDR_RCVD)
Address Received bit If 9Bit
data mode (LCR_EXT[0]=1) is
enabled, This bit is used to
indicate the 9th bit of the
receive data is set to 1. This
bit can also be used to indicate
whether the incoming
character is address or data.
1 = Indicates the character is
address.
0 = Indicates the character is
data.