Datasheet

UART
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
202 Document Number: 333577-002EN
14.3.1.4 Line Control (LCR)
Used to specify the format of the asynchronous data communication exchange.
MEM Offset (B0002000) 0B000200Ch
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bits Access
Type
Default Description PowerWell ResetSignal
31:8 RO 24'b0 Reserved (RSV)
7 RW 1'h0 Divisor Latch Access Bit
(DLAB)
Used to enable reading and
writing of the Divisor Latch
register (DLL and DLH) to set
the baud rate of the UART.
This bit must be cleared after
initial baud rate setup in order
to access other registers.
6 RW 1'h0 Break Control Bit (BC)
Used to cause a break
condition to be transmitted to
the receiving device. If set to
one the serial output is forced
to the spacing (logic 0) state.
When not in Loopback Mode,
as determined by MCR[4], the
sout line is forced low until the
Break bit is cleared.
5 RW 1'h0 Reserved for future use
(STICK_PAR)
4 RW 1'h0 Even Parity Select (EPS)
Used to select between even
and odd parity, when parity is
enabled (PEN set to one). If
set to one, an even number of
logic '1's is transmitted or
checked. If set to zero, an odd
number of logic '1's is
transmitted or checked.
3 RW 1'h0 Parity Enable (PEN)
Used to enable and disable
parity generation and
detection in transmitted and
received serial character
respectively.
0 = parity disabled
1 = parity enabled