Datasheet

UART
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 201
Bits Access
Type
Default Description PowerWell ResetSignal
Resets the control portion of
the transmit FIFO and treats
the FIFO as empty. This will
also de-assert the DMA TX
request and single signals.
NOTE that this bit is 'self-
clearing' and it is not
necessary to clear this bit.
3 DMAM, DMA Mode
4-5 TET, TX Empty Trigger
Used to select the empty
threshold level at which the
THRE Interrupts will be
generated when the mode is
active. It also determines
when the dma_tx_req_n signal
will be asserted when in
certain modes of operation.
The following trigger levels are
supported:
00 = FIFO empty
01 = 2 characters in the FIFO
10 = FIFO 1/4 full
11 = FIFO 1/2 full
6-7 RT, RCVR Trigger
Used to select the trigger level
in the receiver FIFO at which
the Received Data Available
Interrupt will be generated. In
auto flow control mode it is
used to determine when the
rts_n signal will be de-
asserted. It also determines
when the dma_rx_req_n
signal will be asserted when in
certain modes of operation.
The following trigger levels are
supported:
00 = 1 character in the FIFO
01 = FIFO 1/4 full
10 = FIFO 1/2 full
11 = FIFO 2 less than full