Datasheet

UART
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
200 Document Number: 333577-002EN
Bits Access
Type
Default Description PowerWell ResetSignal
0000 = modem status.
0001 = no interrupt pending.
0010 = THR empty.
0100 = received data
available.
0110 = receiver line status.
0111 = busy detect. NEVER
INDICATED
1100 = character timeout.
4-5 RESERVED read as zero
6-7 FIFOSE, FIFOs Enabled.
This is used to indicate
whether the FIFO's are
enabled or disabled:
00 = disabled
11 = enabled
RESET VALUE FOR IIR = 0x01
FCR, FIFO Control Register
Access - Write only
Used to control the FIFOs.
Different functions:
0 FIFOE, FIFO Enable.
Enables/disables the transmit
(XMIT) and receive (RCVR)
FIFO's. Whenever the value of
this bit is changed both the
XMIT and RCVR controller
portion of FIFO's will be reset.
1 RFIFOR, RCVR FIFO Reset
Resets the control portion of
the receive FIFO and treats
the FIFO as empty. This will
also de-assert the DMA RX
request and single signals.
NOTE that this bit is 'self-
clearing' and it is not
necessary to clear this bit.
2 XFIFOR, XMIT FIFO Reset