Datasheet

UART
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 199
Bits Access
Type
Default Description PowerWell ResetSignal
This register makes up the
upper 8-bits of a 16-bit,
read/write, Divisor Latch
register that contains the baud
rate divisor for the UART. This
register may only be accessed
when the DLAB bit (LCR[7]) is
set. This register may be
accessed only when the DLAB
bit (LCR[7]) is set. Note that
with the Divisor Latch
Registers (DLL and DLH) set to
zero, the baud clock is
disabled and no serial
communications occur. Also,
once the DLL is set, at least 8
clock cycles of sclk should be
allowed to pass before
transmitting or receiving data.
14.3.1.3 Interrupt Identification / FIFO Control (IIR_FCR)
Interrupt Identification Register (IIR) if reading; FIFO Control Register (FCR) if
writing.
MEM Offset (B0002000) 0B0002008h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0001h
Bits Access
Type
Default Description PowerWell ResetSignal
31:8 RO 24'b0 Reserved (RSV)
7:0 RW 8'h01 Interrupt Identification /
FIFO Control (FIELD)
Different UART registers are
accessed depending on
read/write transfer type.
IIR, Interrupt Identification
Register
Access - Read only
Each of the bits used has a
different function:
0-3 IID, Interrupt ID. This
indicates the highest priority
pending interrupt which can be
one of the following types: