Datasheet

UART
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 195
14.3 Memory Mapped IO Registers
Registers listed are for UART 0 or UART A, starting at base address B0002000h. UART
1 or UART B contains the same registers starting at base address B0002400h.
Differences between the UARTs are noted in individual registers.
Table 34. Summary of UART Registers—0xB0002000
MEM
Address
Default Instance Name Name
0xB0002000 0000_0000h RBR_THR_DLL Receive Buffer / Transmit Holding / Divisor Latch
Low
0xB0002004 0000_0000h IER_DLH Interrupt Enable / Divisor Latch High
0xB0002008 0000_0001h IIR_FCR Interrupt Identification / FIFO Control
0xB000200C 0000_0000h LCR Line Control
0xB0002010 0000_0000h MCR MODEM Control
0xB0002014 0000_0060h LSR Line Status
0xB0002018 0000_0000h MSR MODEM Status
0xB000201C 0000_0000h SCR Scratchpad
0xB000207C 0000_0000h USR UART Status
0xB00020A4 0000_0000h HTX Halt Transmission
0xB00020A8 0000_0000h DMASA DMA Software Acknowledge
0xB00020AC 0000_0006h TCR Transceiver Control Register
0xB00020B0 0000_0000h DE_EN Driver Output Enable Register
0xB00020B4 0000_0000h RE_EN Receiver Output Enable Register
0xB00020B8 0000_0000h DET Driver Output Enable Timing Register
0xB00020BC 0000_0000h TAT TurnAround Timing Register
0xB00020C0 0000_0000h DLF Divisor Latch Fraction
0xB00020C4 0000_0000h RAR Receive Address Register
0xB00020C8 0000_0000h TAR Transmit Address Register
0xB00020CC 0000_0000h LCR_EXT Line Extended Control Register