Datasheet
I2C
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 189
Bit
s
Acces
s
Type
Defaul
t
Description PowerWe
ll
ResetSign
al
When read as 1, the controller is
deemed to have forced a NACK
during any part of an I2C
transfer, irrespective of whether
the I2C address matches the
slave address (IC_SAR register)
OR if the transfer is completed
before IC_ENABLE is set to 0 but
has not taken effect. NOTE: If
the remote I2C master
terminates the transfer with a
STOP condition before the
controller has a chance to NACK
a transfer, and IC_ENABLE has
been set to 0, then this bit will
also be set to 1. When read as 0,
controller is deemed to have
been disabled when there is
master activity, or when the I2C
bus is idle. NOTE: The CPU can
safely read this bit when IC_EN
(bit 0) is read as 0.
0 RO 1'b0 I2C Enable Status (IC_EN)
When read as 1, the controller is
deemed to be in an enabled
state. When read as 0, the
controller is deemed completely
inactive.
NOTE: The CPU can safely read
this bit anytime. When this bit is
read as 0, the CPU can safely
read SLV_RX_DATA_LOST (bit 2)
and
SLV_DISABLED_WHILE_BUSY
(bit 1).
13.3.1.40 SS and FS Spike Suppression Limit (IC_FS_SPKLEN)
Used to store the duration, measured in I2C clock cycles, of the longest spike that is
filtered out by the spike suppression logic when the component is operating in
Standard/Fast Speed modes. The relevant I2C requirement is detailed in the I2C Bus
Specification. This register must be programmed with a minimum value of 2.
MEM Offset () 0B00028A0h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0007h