Datasheet
I2C
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
188 Document Number: 333577-002EN
Bit
s
Acces
s
Type
Defaul
t
Description PowerWe
ll
ResetSign
al
Indicates if a Slave-Receiver
operation has been aborted with
at least one data byte received
from an I2C transfer due to the
setting of IC_ENABLE from 1 to
0. When read as 1, the I2C
controller is deemed to have
been actively engaged in an
aborted I2C transfer (with
matching address) and the data
phase of the I2C transfer has
been entered, even though a
data byte has been responded
with a NACK. NOTE: If the
remote I2C master terminates
the transfer with a STOP
condition before the controller
has a chance to NACK a transfer,
and IC_ENABLE has been set to
0, then this bit is also set to 1.
When read as 0, the controller is
deemed to have been disabled
without being actively involved in
the data phase of a Slave-
Receiver transfer. NOTE: The
CPU can safely read this bit when
IC_EN (bit 0) is read as 0.
1 RO 1'b0 Slave Disabled While Busy
(SLV_DISABLED_WHILE_BUS
Y)
This bit indicates if a potential or
active Slave operation has been
aborted due to the setting of the
IC_ENABLE register from 1 to 0.
This bit is set when the CPU
writes a 0 to the IC_ENABLE
register while:
(a) the I2C controller is receiving
the address byte of the Slave-
Transmitter operation from a
remote master; OR, (b) address
and data bytes of the Slave-
Receiver operation from a
remote master.