Datasheet

I2C
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
186 Document Number: 333577-002EN
Bits Access
Type
Default Description PowerWell ResetSignal
The watermark level =
DMARDL+1, signal is
generated when the number of
valid data entries in the
receive FIFO is equal to or
more than this field value + 1,
and RDMAE = 1.
13.3.1.37 SDA Setup (IC_SDA_SETUP)
Controls the amount of time delay (in terms of number of I2C clock periods)
introduced in the rising edge of SCL relative to SDA changing, by holding SCL low
when servicing a read request while operating as a slave-transmitter. This register
must be programmed with a value equal to or greater than 2.
MEM Offset () 0B0002894h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0064h
Bits Access
Type
Default Description PowerWell ResetSignal
31:8 RO 24'b0 Reserved (RSV)
7:0 RW 8'h64 SDA Setup (SDA_SETUP)
It is recommended that if the
required delay is 1us, then for
an I2C clock frequency of 10
MHz, IC_SDA_SETUP should
be programmed to a value of
11.