Datasheet

I2C
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 185
13.3.1.35 DMA Transmit Data Level Register (IC_DMA_TDLR)
MEM Offset () 0B000288Ch
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bits Access
Type
Default Description PowerWell ResetSignal
31:5 RO 27'b0 Reserved (RSV)
4:0 RW 5'h0 Transmit Data Level
(DMATDL)
Receive Data Level. This bit
field controls the level at
which a DMA request is made
by the receive logic.
It is equal to the watermark
level, signal generated when
the number of valid data
entries in the transmit FIFO is
equal to or below this field
value, and TDMAE = 1.
13.3.1.36 I2C Receive Data Level Register (IC_DMA_RDLR)
MEM Offset () 0B0002890h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bits Access
Type
Default Description PowerWell ResetSignal
31:5 RO 27'b0 Reserved (RSV)
4:0 RW 5'h0 Receive Data Level
(DMARDL)
This bit field controls the level
at which a DMA
request is made by the receive
logic.