Datasheet

I2C
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
182 Document Number: 333577-002EN
Bits Acces
s Type
Defaul
t
Description PowerWel
l
ResetSigna
l
Set if master has lost
arbitration, or if
IC_TX_ABRT_SOURCE[14] is
also set, then the slave
transmitter has lost
arbitration. Note: I2C can be
both master and slave at the
same time.
11 RO 1'b0 Master Disabled
(ABRT_MASTER_DIS)
Set if user tries to initiate a
Master operation with the
Master mode disabled.
10 RO 1'b0 10 Bit Address READ and
RESTART Disabled
(ABRT_10B_RD_NORSTRT
)
Set if the restart is disabled
(IC_RESTART_EN bit
(IC_CON[5]) =0) and the
master sends a read
command in 10-bit
addressing mode.
9 RO 1'b0 START With RESTART
Disabled
(ABRT_SBYTE_NORSTRT)
To clear Bit 9, the source of
the ABRT_SBYTE_NORSTRT
must be fixed first; restart
must be enabled
(IC_CON[5]=1), the SPECIAL
bit must be cleared
(IC_TAR[11]), or the
GC_OR_START bit must be
cleared (IC_TAR[10]). Once
the source of the
ABRT_SBYTE_NORSTRT is
fixed, then this bit can be
cleared in the same manner
as other bits in this register.
If the source of the
ABRT_SBYTE_NORSTRT is not
fixed before attempting to
clear this bit, bit 9 clears for
one cycle and then gets
reasserted. Set if the restart
is disabled (IC_RESTART_EN
bit (IC_CON[5]) =0) and the
user is trying to send a
START Byte.
8 RO 1'b0 HS Mode With RESTART
Disabled
(ABRT_HS_NORSTRT)