Datasheet
I2C
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 181
Bits Acces
s Type
Defaul
t
Description PowerWel
l
ResetSigna
l
31:2
3
RO 9'b0 Reserved
(TX_FLUSH_CNT)
22:1
7
RO 6'b0 Reserved (RSV)
16 RO 1'b0 ABRT_USER_ABRT
(ABRT_USER_ABRT)
This is a master-mode-only
bit. Master has detected the
transfer abort
(IC_ENABLE[1]).
15 RO 1'b0 Slave Read Completion
(ABRT_SLVRD_INTX)
Set if the processor side
responds to a slave mode
request for data to be
transmitted to a remote
master and user writes a 1 in
CMD (bit 8) of IC_DATA_CMD
register.
14 RO 1'b0 Slave Lost Bus
(ABRT_SLV_ARBLOST)
Set if slave lost the bus while
transmitting data to a remote
master.
IC_TX_ABRT_SOURCE[12] is
set at the same time. Note:
Even though the slave never
'owns' the bus, something
could go wrong on the bus.
This is a fail safe check. For
instance, during a data
transmission at the low-to-
high transition of SCL, if what
is on the data bus is not what
is supposed to be
transmitted, then I2C
controller no longer own the
bus.
13 RO 1'b0 Slave Flush TX FIFO
(ABRT_SLVFLUSH_TXFIFO
)
Set if slave has received a
read command and some
data exists in the TX FIFO so
the slave issues a TX_ABRT
interrupt to flush old data in
TX FIFO.
12 RO 1'b0 Master Lost Arbitration
(ARB_LOST)