Datasheet

I2C
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
180 Document Number: 333577-002EN
13.3.1.32 SDA Hold (IC_SDA_HOLD)
This register controls the amount of hold time on the SDA signal after a negative edge
of SCL line in units of I2C clock period. The value programmed must be greater than
the minimum hold time in each mode for the value to be implemented: 1 cycle in
master, 7 cycles in slave mode. Writes to this register succeed only when I2C
controller is disabled (IC_ENABLE=0).
MEM Offset () 0B000287Ch
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0001_0001h
Bits Access
Type
Default Description PowerWell ResetSignal
31:24 RO 8'b0 Reserved (RSV)
23:16 RW 8'h1 SDA Hold
(IC_SDA_RX_HOLD)
Sets the required SDA hold
time in units of IC_CLK
period, when I2C controller
acts as a transmitter.
15:0 RW 16'h1 IC_SDA_TX_HOLD
(IC_SDA_TX_HOLD)
Sets the required SDA hold
time in units of IC_CLK
period, when I2C controller
acts as a receiver.
13.3.1.33 Transmit Abort Source (IC_TX_ABRT_SOURCE)
Used to indicate the source of the TX_ABRT interrupt. Except for Bit 9, this register is
cleared whenever the IC_CLR_TX_ABRT register or the IC_CLR_INTR register is read.
To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; RESTART
must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or
the GC_OR_START bit must be cleared (IC_TAR[10]). Once the source of the
ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as
other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed
before attempting to clear this bit, Bit 9 clears for one cycle and is then re-asserted.
MEM Offset () 0B0002880h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h