Datasheet
Introduction
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
18 Document Number: 333577-002EN
• Supports HW DMA with configurable FIFO thresholds
• Supports 9-bit serial operation mode
• Supports RS485
• Support for DTR/DCD/DSR/RI Modem Control Pins through GPIO pins controlled
by Software
1.1.6 SPI
• One SPI Master Interfaces with support for SPI clock frequencies up to 16 MHz
• One SPI Slave Interface with support for SPI clock frequencies up to 3.2 MHz
• Support for 4-bit up to 32-bit Frame Size
• Up to four Slave Select pins per Master interface
• FIFO mode support (Independent 32B TX and RX FIFO’s)
• Supports HW DMA with configurable FIFO thresholds
1.1.7 DMA Controller
• Provides 2 Unidirectional Channels
• Provides support for 16 HW Handshake Interfaces
o tx and rx channels of I
2
C controller, SPI Slave controller, SPI Master
controller, two UART controllers use this interface
• Supports Memory to Memory, Peripheral to Memory, Memory to Peripheral and
Peripheral to Peripheral transfers
• Dedicated Hardware Handshaking interfaces with peripherals plus Software
Handshaking Support
• Supports Single and Multi-Block Transfers
1.1.8 GPIO Controller
• Provides 25 independently configurable GPIO
• All GPIOs are interrupt capable supporting level sensitive and edge triggered
modes
• Debounce logic for interrupt source
• All 25 GPIOs are Always-on interrupt and wake capable
1.1.9 Timers
• Two 32-bit Timers running at system clock (running in timer mode or PWM mode)
• Supports an additional 32-bit Always-On Counter running with 32.768 kHz clock
• Supports an additional 32-bit Always-On Periodic Timer running with 32.768 kHz
clock and with interrupt and wake capability
1.1.10 Pulse Width Modulation (PWM)
• Two 32-bit Timers running at system clock can be configured to generate two
PWM outputs