Datasheet

I2C
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 179
13.3.1.30 Transmit FIFO Level (IC_TXFLR)
Contains the number of valid data entries in the transmit FIFO buffer.
It is cleared whenever: The I2C is disabled, there is a transmit abort
( i.e. TX_ABRT bit is set in the IC_RAW_INTR_STAT register ) or the slave bulk
transmit mode is aborted.
The register increments whenever data is placed into the transmit FIFO and
decrements when data is taken from the transmit FIFO.
MEM Offset () 0B0002874h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bits Access
Type
Default Description PowerWell ResetSignal
31:5 RO 27'b0 Reserved (RSV)
4:0 RO 5'b0 Transmit FIFO Level
(TXFLR)
Contains the number of valid
data entries in the transmit
FIFO.
13.3.1.31 Receive FIFO Level (IC_RXFLR)
This register contains the number of valid data entries in the receive FIFO buffer.
It is cleared whenever: The I2C is disabled, whenever there is a transmit abort caused
by any of the events tracked in IC_TX_ABRT_SOURCE.
The register increments whenever data is placed into the receive FIFO and
decrements when data is taken from the receive FIFO.
MEM Offset () 0B0002878h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bits Access
Type
Default Description PowerWell ResetSignal
31:5 RO 27'b0 Reserved (RSV)
4:0 RO 5'b0 Receive FIFO Level
(RXFLR)
Contains the number of valid
data entries in the receive
FIFO.