Datasheet

I2C
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
178 Document Number: 333577-002EN
Bits Access
Type
Default Description PowerWell ResetSignal
NOTE: IC_STATUS[0]-that is,
ACTIVITY bit-is the OR of
SLV_ACTIVITY and
MST_ACTIVITY bits.
4 RO 1'b0 Receive FIFO Completely
Full (RFF)
When the receive FIFO is
completely full, this bit is set.
When the receive FIFO
contains one or more empty
location, this bit is cleared.
0: Receive FIFO is not full
1: Receive FIFO is full
3 RO 1'b0 Receive FIFO Not Empty
(RFNE)
This bit is set when the receive
FIFO contains one or more
entries; it is cleared when the
receive FIFO is empty.
0: Receive FIFO is empty
1: Receive FIFO is not empty
2 RO 1'b1 Transmit FIFO Completely
Empty (TFE)
When the transmit FIFO is
completely empty, this bit is
set. When it contains one or
more valid entries, this bit is
cleared. This bit field does not
request an interrupt.
0: Transmit FIFO is not empty
1: Transmit FIFO is empty
1 RO 1'b1 Transmit FIFO Not Full
(TFNF)
Set when the transmit FIFO
contains one or more empty
locations, and is cleared when
the FIFO is full.
0: Transmit FIFO is full
1: Transmit FIFO is not full
0 RO 1'b0 Activity (ACTIVITY)
Receive FIFO Not Empty. This
bit is set when the receive
FIFO contains one or more
entries; it is cleared when the
receive FIFO is empty.
0: Receive FIFO is empty
1: Receive FIFO is not empty