Datasheet

I2C
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 177
Bits Access
Type
Default Description PowerWell ResetSignal
If the module is receiving, the
controller stops the current
transfer at the end of the
current byte and does not
acknowledge the transfer.
There is a two I2C clocks delay
when enabling or disabling the
controller.
13.3.1.29 Status (IC_STATUS)
Read-only register used to indicate the current transfer status and FIFO status. The
status register may be read at any time. None of the bits in this register request an
interrupt. When the I2C is disabled by writing 0 in bit 0 of the IC_ENABLE register:
bits 1 and 2 are set to 1, bits 3 and 4 are set to 0.
When the master or slave state machines goes to idle and IC_EN=0: bits 5 and 6 are
set to 0.
MEM Offset () 0B0002870h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0006h
Bits Access
Type
Default Description PowerWell ResetSignal
31:7 RO 25'b0 Reserved (RSV)
6 RO 1'b0 SLV_ACTIVITY
(SLV_ACTIVITY)
When the Slave Finite State
Machine (FSM) is not in the
IDLE state, this bit is set.
0: Slave FSM is in IDLE state
so the Slave part is not Active
1: Slave FSM is not in IDLE
state so the Slave part is
Active
5 RO 1'b0 Master FSM Activity Status
(MST_ACTIVITY)
When the Master Finite State
Machine (FSM) is not in the
IDLE state, this bit is set.
0: Master FSM is in IDLE state
so the Master part is not
Active
1: Master FSM is not in IDLE
state so the Master part is
Active