Datasheet

I2C
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
176 Document Number: 333577-002EN
Bits Access
Type
Default Description PowerWell ResetSignal
The software can abort the
I2C transfer in master mode
by setting this bit. The
software
can set this bit only when
ENABLE is already set;
otherwise, the controller
ignores any
write to ABORT bit. The
software cannot clear the
ABORT bit once set. In
response to
an ABORT, the controller
issues a STOP and flushes the
Tx FIFO after completing the
current transfer, then sets the
TX_ABORT interrupt after the
abort operation. The
ABORT bit is cleared
automatically after the abort
operation.
When set, the controller
initiates the transfer abort.
0: ABORT not initiated or
ABORT done
1: ABORT operation in
progress
0 RW 1'b0 Enable I2C Controller
(ENABLE)
0: Disabled (TX/RX FIFOs are
held in an erased state)
1: Enabled
NOTE: ensure that the
controller is disabled properly.
When disabled, the following
occurs:
- The TX FIFO and RX FIFO get
flushed.
- Status bits in the
IC_INTR_STAT register are
still active until the I2C
Controller goes into IDLE
state.
If the module is transmitting,
it stops as well as deletes the
contents of the transmit buffer
after the current transfer is
complete.