Datasheet

I2C
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
168 Document Number: 333577-002EN
Bits Access
Type
Default Description PowerWell ResetSignal
Set when the receive buffer
reaches or goes above the
RX_TL threshold in the
IC_RX_TL register. It is
automatically cleared by
hardware when buffer level
goes below the threshold. If
the module is disabled
(IC_ENABLE[0]=0), the RX
FIFO is flushed and held in
reset; therefore the RX FIFO
is not full. So this bit is
cleared once the IC_ENABLE
bit 0 is programmed with a 0,
regardless of the activity that
continues.
1 RO 1'b0 RX Overflow (RX_OVER)
Set if the receive buffer is
completely filled to
IC_RX_BUFFER_DEPTH and
an additional byte is received
from an external I2C device.
The I2C Controller
acknowledges this, but any
data bytes received after the
FIFO is full are lost. If the
module is disabled
(IC_ENABLE[0]=0), this bit
keeps its level until the
master or slave state
machines go into idle, and
when IC_EN goes to 0, this
interrupt is cleared.
0 RO 1'b0 RX Underflow
(RX_UNDER)
Set if the processor attempts
to read the receive buffer
when it is empty by reading
from the IC_DATA_CMD
register. If the module is
disabled (IC_ENABLE[0]=0),
this bit keeps its level until
the master or slave state
machines go into idle, and
when IC_EN goes to 0, this
interrupt is cleared.