Datasheet

I2C
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
166 Document Number: 333577-002EN
Bits Access
Type
Default Description PowerWell ResetSignal
Once this bit is set, it stays
set unless one of the four
methods is used to clear it.
Even if the controller is idle,
this bit remains set until
cleared, indicating that there
was activity on the bus.
7 RO 1'b0 RX Completed (RX_DONE)
When the I2C controller is
acting as a slave-transmitter,
this bit is set to 1 if the
master does not acknowledge
a transmitted byte. This
occurs on the last byte of the
transmission, indicating that
the transmission is done.
6 RO 1'b0 TX Abort (TX_ABRT)
This bit indicates if the I2C
controller, in transmitter
mode, is unable to complete
the intended actions on the
contents of the transmit
FIFO. This situation can occur
both as an I2C master or an
I2C slave, and is referred to
as a 'transmit abort'. When
this bit is set to 1, the
IC_TX_ABRT_SOURCE
register indicates the reason
why the transmit abort takes
places.
NOTE: The controller
flushes/resets/empties the
TX FIFO whenever this bit is
set. The TX FIFO remains in
this flushed state until the
register IC_CLR_TX_ABRT is
read. Once this read is
performed, the TX FIFO is
then ready to accept more
data bytes for transmission.
5 RO 1'b0 Read Requested
(RD_REQ)