Datasheet

I2C
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
164 Document Number: 333577-002EN
Bits Access
Type
Default Description PowerWell ResetSignal
Set if the receive buffer is
completely filled to
IC_RX_BUFFER_DEPTH and
an additional byte is received
from an external I2C device.
The I2C Controller
acknowledges this, but any
data bytes received after the
FIFO is full are lost. If the
module is disabled
(IC_ENABLE[0]=0), this bit
keeps its level until the
master or slave state
machines go into idle, and
when IC_EN goes to 0, this
interrupt is cleared.
0 RW 1'b1 RX Underflow Mask
(M_RX_UNDER)
Set if the processor attempts
to read the receive buffer
when it is empty by reading
from the IC_DATA_CMD
register. If the module is
disabled (IC_ENABLE[0]=0),
this bit keeps its level until
the master or slave state
machines go into idle, and
when IC_EN goes to 0, this
interrupt is cleared.
13.3.1.14 Raw Interrupt Status (IC_RAW_INTR_STAT)
Unlike the IC_INTR_STAT register, these bits are not masked so they always show the
true status of the I2C controller.
MEM Offset () 0B0002834h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bits Access
Type
Default Description PowerWell ResetSignal
31:13 RO 19'b0 Reserved (RSV)
12 RO 1'b0 RESTART condition has
occurred (RESTART_DET)