Datasheet

I2C
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 163
Bits Access
Type
Default Description PowerWell ResetSignal
This bit is set to 1 when the
transmit buffer is at or below
the threshold value set in the
IC_TX_TL register. It is
automatically cleared by
hardware when the buffer
level goes above the
threshold. When the
IC_ENABLE bit 0 is 0, the TX
FIFO is flushed and held in
reset. There the TX FIFO
looks like it has no data
within it, so this bit is set to
1, provided there is activity
in the master or slave state
machines. When there is no
longer activity, then with
IC_EN=0, this bit is set to 0.
Reset value.
3 RW 1'b1 TX Overflow Mask
(M_TX_OVER)
Set during transmit if the
transmit buffer is filled to
IC_TX_BUFFER_DEPTH and
the processor attempts to
issue another I2C command
by writing to the
IC_DATA_CMD register.
When the module is disabled,
this bit keeps its level until
the master or slave state
machines go into idle, and
when IC_EN goes to 0, this
interrupt is cleared.
2 RW 1'b1 RX Full Mask
(M_RX_FULL)
Set when the receive buffer
reaches or goes above the
RX_TL threshold in the
IC_RX_TL register. It is
automatically cleared by
hardware when buffer level
goes below the threshold. If
the module is disabled
(IC_ENABLE[0]=0), the RX
FIFO is flushed and held in
reset; therefore the RX FIFO
is not full. This bit is cleared
once the IC_ENABLE bit 0 is
programmed with a 0,
regardless of the activity that
continues.
1 RW 1'b1 RX Overflow Mask
(M_RX_OVER)