Datasheet

I2C
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
162 Document Number: 333577-002EN
Bits Access
Type
Default Description PowerWell ResetSignal
This bit indicates if the I2C
controller, in transmitter
mode, is unable to complete
the intended actions on the
contents of the transmit
FIFO. This situation can occur
both as an I2C master or an
I2C slave, and is referred to
as a 'transmit abort'. When
this bit is set to 1, the
IC_TX_ABRT_SOURCE
register indicates the reason
why the transmit abort takes
places.
NOTE: The controller
flushes/resets/empties the
TX FIFO whenever this bit is
set. The TX FIFO remains in
this flushed state until the
register IC_CLR_TX_ABRT is
read. Once this read is
performed, the TX FIFO is
then ready to accept more
data bytes for transmission.
5 RW 1'b1 Read Requested Mask
(M_RD_REQ)
This bit is set to 1 when I2C
controller is acting as a slave
and another I2C master is
attempting to read data from
it. The controller holds the
I2C bus in a wait state
(SCL=0) until this interrupt is
serviced, which means that
the slave has been addressed
by a remote master that is
asking for data to be
transferred. The processor
must respond to this
interrupt and then write the
requested data to the
IC_DATA_CMD register. This
bit is set to 0 just after the
processor reads the
IC_CLR_RD_REQ register.
4 RW 1'b1 TX Empty Mask
(M_TX_EMPTY)