Datasheet

I2C
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
160 Document Number: 333577-002EN
Bits Access
Type
Default Description PowerWell ResetSignal
Set if the processor attempts
to read the receive buffer
when it is empty by reading
from the IC_DATA_CMD
register. If the module is
disabled (IC_ENABLE[0]=0),
this bit keeps its level until
the master or slave state
machines go into idle, and
when IC_EN goes to 0, this
interrupt is cleared.
13.3.1.13 Interrupt Mask (IC_INTR_MASK)
These bits mask their corresponding interrupt status bits. They are active high; a
value of 0 prevents a bit from generating an interrupt.
MEM Offset () 0B0002830h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_18FFh
Bits Access
Type
Default Description PowerWell ResetSignal
31:13 RO 19'b0 Reserved (RSV)
12 RW 1'b1 M_RESTART_DET Mask
(M_RESTART_DET)
This bit masks the
R_RESTART_DET interrupt
status bit in the
IC_INTR_STAT register.
11 RW 1'b1 General Call
Acknowledged Mask
(M_GEN_CALL)
Set only when a General Call
address is received and it is
acknowledged. It stays set
until it is cleared either by
disabling the I2C controller or
when the CPU reads bit 0 of
the IC_CLR_GEN_CALL
register. I2C controller stores
the received data in the Rx
buffer.
10 RW 1'b0 Start Detected Mask
(M_START_DET)