Datasheet

I2C
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
158 Document Number: 333577-002EN
Bits Access
Type
Default Description PowerWell ResetSignal
NOTE: The controller
flushes/resets/empties the
TX FIFO whenever this bit is
set. The TX FIFO remains in
this flushed state until the
register IC_CLR_TX_ABRT is
read. Once this read is
performed, the TX FIFO is
then ready to accept more
data bytes for transmission.
5 RO 1'b0 Read Requested
(R_RD_REQ)
This bit is set to 1 when I2C
controller is acting as a slave
and another I2C master is
attempting to read data from
it. The controller holds the
I2C bus in a wait state
(SCL=0) until this interrupt is
serviced, which means that
the slave has been addressed
by a remote master that is
asking for data to be
transferred. The processor
must respond to this
interrupt and then write the
requested data to the
IC_DATA_CMD register. This
bit is set to 0 just after the
processor reads the
IC_CLR_RD_REQ register.
4 RO 1'b0 TX Empty (R_TX_EMPTY)
This bit is set to 1 when the
transmit buffer is at or below
the threshold value set in the
IC_TX_TL register. It is
automatically cleared by
hardware when the buffer
level goes above the
threshold. When the
IC_ENABLE bit 0 is 0, the TX
FIFO is flushed and held in
reset. There the TX FIFO
looks like it has no data
within it, so this bit is set to
1, provided there is activity
in the master or slave state
machines. When there is no
longer activity, then with
ic_en=0, this bit is set to 0.
Reset value.
3 RO 1'b0 TX Overflow (R_TX_OVER)