Datasheet

I2C
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 157
Bits Access
Type
Default Description PowerWell ResetSignal
9 RO 1'b0 Stop Detected
(R_STOP_DET)
Indicates whether a STOP
condition has occurred on the
I2C interface regardless of
whether the controller is
operating in slave or master
mode.
8 RO 1'b0 Activity (R_ACTIVITY)
This bit captures I2C
controller activity and stays
set until it is cleared. There
are four ways to clear it:
- Disabling the controller
- Reading the
IC_CLR_ACTIVITY register
- Reading the IC_CLR_INTR
register
- System reset
Once this bit is set, it stays
set unless one of the four
methods is used to clear it.
Even if the controller is idle,
this bit remains set until
cleared, indicating that there
was activity on the bus
7 RO 1'b0 RX Completed
(R_RX_DONE)
When the I2C controller is
acting as a slave-transmitter,
this bit is set to 1 if the
master does not acknowledge
a transmitted byte. This
occurs on the last byte of the
transmission, indicating that
the transmission is done.
6 RO 1'b0 TX Abort (R_TX_ABRT)
This bit indicates if the I2C
controller, in transmitter
mode, is unable to complete
the intended actions on the
contents of the transmit
FIFO. This situation can occur
both as an I2C master or an
I2C slave, and is referred to
as a 'transmit abort'. When
this bit is set to 1, the
IC_TX_ABRT_SOURCE
register indicates the reason
why the transmit abort takes
places.