Datasheet

I2C
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
156 Document Number: 333577-002EN
Bits Access
Type
Default Description PowerWell ResetSignal
Must be set before any I2C
bus transaction can take
place to ensure proper I/O
timing. For 100pF loading,
the SCL High time is 60ns;
for 400pF loading, the SCL
High time is 120ns.
The minimum valid value is
8; hardware prevents values
less than this being written,
and if attempted results in 8
being set.
13.3.1.12 Interrupt Status (IC_INTR_STAT)
Each bit in this register has a corresponding mask bit in the IC_INTR_MASK register.
These bits are cleared by reading the matching interrupt clear register. The unmasked
raw versions of these bits are available in the IC_RAW_INTR_STAT register.
MEM Offset () 0B000282Ch
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bits Access
Type
Default Description PowerWell ResetSignal
31:12 RO 20'b0 Reserved (RSV)
11 RO 1'b0 General Call
Acknowledged
(R_GEN_CALL)
Set only when a General Call
address is received and it is
acknowledged. It stays set
until it is cleared either by
disabling the I2C controller or
when the CPU reads bit 0 of
the IC_CLR_GEN_CALL
register. I2C controller stores
the received data in the Rx
buffer.
10 RO 1'b0 Start Detected
(R_START_DET)
Indicates whether a START or
RESTART condition has
occurred on the I2C interface
regardless of whether the
controller is operating in
slave or master mode.