Datasheet

I2C
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 155
13.3.1.10 High Speed I2C Clock SCL High Count
(IC_HS_SCL_HCNT)
Sets the SCL clock high-period count for high speed (HS). Can be written only when
the I2C is disabled (IC_ENABLE==0). Writes at other times have no effect.
MEM Offset () 0B0002824h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0006h
Bits Access
Type
Default Description PowerWell ResetSignal
31:16 RO 16'b0 Reserved (RSV)
15:0 RW 16'h0006 HS SCL clock high-period
count (IC_HS_SCL_HCNT)
Must be set before any I2C
bus transaction can take
place to ensure proper I/O
timing. The SCL High time
depends on the loading of
the bus. For 100pF loading,
the SCL High time is 60ns;
for 400pF loading, the SCL
High time is 120ns.
The minimum valid value is
6; hardware prevents values
less than this being written,
and if attempted results in 6
being set.
13.3.1.11 High Speed I2C Clock SCL Low Count
(IC_HS_SCL_LCNT)
Sets the SCL clock low-period count for high speed (HS). Can be written only when
the I2C is disabled (IC_ENABLE==0). Writes at other times have no effect.
MEM Offset () 0B0002828h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0010h
Bits Access
Type
Default Description PowerWell ResetSignal
31:16 RO 16'b0 Reserved (RSV)
15:0 RW 16'h0010 SS SCL clock low-period
count (IC_HS_SCL_LCNT)