Datasheet

I2C
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
152 Document Number: 333577-002EN
13.3.1.6 Standard Speed Clock SCL High Count
(IC_SS_SCL_HCNT)
Sets the SCL clock high-period count for standard speed (SS). Can be written only
when the I2C is disabled (IC_ENABLE==0). Writes at other times have no effect.
MEM Offset () 0B0002814h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0190h
Bits Access
Type
Default Description PowerWell ResetSignal
31:16 RO 16'b0 Reserved (RSV)
15:0 RW 16'h0190 SS SCL clock high-period
count (IC_SS_SCL_HCNT)
Must be set before any I2C
bus transaction can take
place to ensure proper I/O
timing.
The minimum valid value is
6; hardware prevents values
less than this being written,
and if attempted results in 6
being set.
This register must not be
programmed to a value
higher than 65525, because
I2C controller uses a 16-bit
counter to flag an I2C bus
idle condition when this
counter reaches a value of
IC_SS_SCL_HCNT + 10.