Datasheet

I2C
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 151
Bits Access
Type
Default Description PowerWell ResetSignal
When a command is entered
in the TX FIFO, this bit
distinguishes the write and
read commands. In slave-
receiver mode, this bit is a
'don't care' because writes to
this register are not required.
In slave-transmitter mode, a
'0' indicates that CPU data is
to be transmitted and as DAT
or IC_DATA_CMD[7:0].
NOTE: when programming
this bit, attempting to
perform a read operation
after a General Call command
has been sent results in a
TX_ABRT interrupt (bit 6 of
the IC_RAW_INTR_STAT
register), unless bit 11
(SPECIAL) in the IC_TAR
register has been cleared. If
a '1' is written to this bit after
receiving a RD_REQ
interrupt, then a TX_ABRT
interrupt occurs.
NOTE: It is possible that
while attempting a master
I2C read transfer, a RD_REQ
interrupt may have occurred
simultaneously due to a
remote I2C master
addressing I2C controller. In
this type of scenario, the I2C
controller ignores the
IC_DATA_CMD write,
generates a TX_ABRT
interrupt, and waits to
service the RD_REQ
interrupt.
7:0 RW 8'b0 Data Buffer (DAT)
Contains the data to be
transmitted or received on
the I2C bus.
When writing to this register
and want to perform a read,
DAT field is ignored by the
I2C controller.
When reading this register,
DAT return the value of data
received on the I2C controller
interface.