Datasheet

I2C
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
150 Document Number: 333577-002EN
Bits Access
Type
Default Description PowerWell ResetSignal
- 1 if IC_RESTART_EN is 1, a
RESTART is issued before the
data is sent/received
(according to the value of
CMD), regardless of whether
or not the transfer direction
is changing from the previous
command; if
IC_RESTART_EN is 0, a STOP
followed by a START is issued
instead.
- 0 If IC_RESTART_EN is 1, a
RESTART is issued only if the
transfer direction is changing
from the previous command;
if IC_RESTART_EN is 0, a
STOP followed by a START is
issued instead
9 RO 1'b0 Stop Bit Control (STOP)
This bit controls whether a
STOP is issued after the byte
is sent or received:
- 1 STOP is issued after this
byte, regardless of whether
or not the Tx FIFO is empty.
If the Tx FIFO is not empty,
the master immediately tries
to start a new transfer by
issuing a START and
arbitrating for the bus.
- 0 STOP is not issued after
this byte, regardless of
whether or not the Tx FIFO is
empty. If the Tx FIFO is not
empty, the master continues
the current transfer by
sending/receiving data bytes
according to the value of the
CMD bit. If the Tx FIFO is
empty, the master holds the
SCL line low and stalls the
bus until a new command is
available in the Tx FIFO.
8 RW 1'b0 Command (CMD)
This bit controls whether a
read or a write is performed.
This bit controls the direction
only in I2C master mode.
0 = Write
1 = Read