Datasheet

I2C
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 149
13.3.1.4 High Speed Master ID (IC_HS_MADDR)
I2C High Speed Master Mode Code Address. Can be written only when the I2C is
disabled (IC_ENABLE==0). Writes at other times have no effect.
MEM Offset () 0B000280Ch
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0001h
Bits Access
Type
Default Description PowerWell ResetSignal
31:3 RO 29'b0 Reserved (RSV)
2:0 RW 3'b01 HS Master Code
(IC_HS_MAR)
This bit field holds the value of
the I2C HS mode master code.
HS-mode master codes are
reserved 8-bit codes
(00001xxx) that are not used
for slave addressing or other
purposes. Each master has its
unique master code; up to
eight high-speed mode
masters can be present on the
same I2C bus system.
Valid values are from 0 to 7.
13.3.1.5 Data Buffer and Command (IC_DATA_CMD)
CPU writes to it when filling the TX FIFO and the reads from when retrieving bytes
from RX FIFO.
MEM Offset () 0B0002810h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bits Access
Type
Default Description PowerWell ResetSignal
31:11 RO 21'b0 Reserved (RSV)
10 RO 1'b0 Restart Bit Control
(RESTART)
This bit controls whether a
RESTART is issued before the
byte is sent or received.