Datasheet

I2C
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
148 Document Number: 333577-002EN
Bits Acces
s Type
Default Description PowerWel
l
ResetSigna
l
This is the target address for
any master transaction.
When transmitting a General
Call, these bits are ignored.
To generate a START BYTE,
the CPU needs to write only
once into these bits.
If the IC_TAR and IC_SAR
are the same, loopback
exists but the FIFOs are
shared between master and
slave, so full loopback is not
feasible. Only one direction
loopback mode is supported
(simplex), not duplex. A
master cannot transmit to
itself; it can transmit to only
a slave.
IMPORTANT: if
MASTER_MODE == 1 -->
IC_SLAVE_DISABLE == 1
13.3.1.3 Slave Address (IC_SAR)
Holds the slave address when the I2C is operating as a slave. Can be written only
when the I2C is disabled (IC_ENABLE==0). Writes at other times have no effect
MEM Offset () 0B0002808h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0055h
Bits Access
Type
Default Description PowerWell ResetSignal
31:10 RO 22'b0 Reserved (RSV)
9:0 RW 10'h055 Slave Address (IC_SAR)
For 7-bit addressing, only
IC_SAR[6:0] is used.