Datasheet

I2C
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
146 Document Number: 333577-002EN
Bits Acces
s Type
Defaul
t
Description PowerWel
l
ResetSigna
l
3 RW 1'b1 Slave Addressing Mode
(IC_10BITADDR_SLAVE)
When acting as a slave, this
bit controls whether the I2C
controller responds to 7- or
10-bit addresses.
- 0: 7-bit addressing
ignores transactions that
involve 10-bit addressing; for
7-bit addressing, only the
lower 7 bits of the IC_SAR
register are compared
- 1: 10-bit addressing
responds to only 10-bit
addressing transfers that
match the full 10 bits of the
IC_SAR register
2:1 RW 2'b11 Speed Mode (SPEED)
I2C Master operational speed.
Relevant only in master mode.
Mode must be set by
firmware.
01: standard mode (100
kbit/s)
10: fast mode (400 kbit/s)
0 RW 1'b1 Master Mode Enable
(MASTER_MODE)
This bit controls whether the
I2C master is enabled.
0: master disabled
1: master enabled
NOTE: Software must ensure
master and slave mode are
mutually exclusive
if MASTER_MODE == 1 -->
IC_SLAVE_DISABLE == 1
13.3.1.2 Master Target Address (IC_TAR)
Can be written only when the I2C is disabled (IC_ENABLE==0). Writes at other times
have no effect.
MEM Offset () 0B0002804h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_2055h